seventeen. The equipment for detecting clock tampering as outlined in assert 15, whereby the Examine circuit is activated by a clock edge at an stop on the clock evaluate time frame.

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delaying the monotone sign employing Every from the plurality of resettable hold off line segments to produce a respective plurality of delayed monotone indicators Just about every getting either a one or possibly a zero logic value; and

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26. The method for detecting voltage tampering as defined in claim 23, wherein the Appraise circuit decides no matter whether the amount of ones inside the plurality of delayed monotone signals differs from a drinking water degree range by more than a predetermined threshold.

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delaying the monotone sign applying Just about every on the plurality of resettable hold off line segments to create a respective plurality of delayed monotone indicators Every owning either a a person or possibly a zero logic price; and

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Disclosed is a technique for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable hold off line segments between a resettable delay line segment associated with a minimum amount hold off time and a resettable delay line phase linked to a most delay time are Every affiliated with discretely rising delay situations.

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12. The apparatus for detecting clock tampering as outlined in declare 11, wherein the water stage number is set according to delayed monotone alerts from one or more preceding clock more info Examine time.

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40. The equipment for detecting voltage tampering as outlined in declare 37, wherein the Examine circuit decides irrespective of whether the amount of ones in the plurality of delayed monotone indicators differs from the water level quantity by over a predetermined threshold to detect the voltage fault.

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